Bias control for transistor circuits incorporating substrate bias generators

ABSTRACT

Control circuitry for sensing excessive substrate bias voltage in a circuit, such as an LSI N-channel MOS transistor circuit incorporating a substrate bias generator, and for maintaining an optimum bias voltage level by bypassing the excess to ground.

BRIEF SUMMARY OF THE INVENTION

This invention relates to voltage control circuits and particularly tocontrol circuitry that senses and limits the bias voltage applied tosubstrates of transistor circuitry.

Most transistor circuits, such as MOS transistor circuits, require anegative bias voltage applied to the circuitry substrate. For largescale circuits, it is a recent development to incorporate an on-chipbias voltage generator, thus enabling the condensation of an entire MOSdevice into one discrete chip requiring only a single input supplyvoltage terminal. In the typical N-channel transistor circuit board, abias generator is required to provide a negative voltage of, forexample, two to four volts on the substrate bias.

The required bias voltage for a circuit is roughly proportional to theapplied V_(cc) supply voltage. For example, a maximum operating supplyvoltage of six volts may require negative substrate bias voltage of fourvolts, whereas a minimum supply voltage of four volts may require alower negative bias voltage of perhaps three volts for proper operationof the associated transistor circuits. Unfortunately, when thetransistors and associated circuitry are dynamically operated bysubjecting them to on-off switching at a relatively high frequency, someof the components subjected to the switching will become more negativethan the substrate and will therefore inject electron charges into thesubstrate to thereby increase the negative bias level on the substrate.The resulting increased bias results in a detrimental reduction in thetransistor drain current by effectively pinching off the channelsbetween the transistor depletion layers, that is, the results areessentially the same as a reduction of the control voltage on the gateelement toward the point of transistor cutoff.

The substrate voltage generator incorporated in a circuit chip operatesfrom the V_(cc) input supply voltage applied to the chip and, aspreviously mentioned, produces a negative bias voltage which, within theV_(cc) operating range, is approximately proportional to the V_(cc)level. The bias control circuitry of the invention therefore measuresthe V_(cc) supply voltage level and applies a voltage input signal ofapproximately one-tenth the measured level to a gating or sensingcircuit, the conduction threshold of which is dependent upon the levelof the substrate bias. If the sensing circuit input of one-tenth V_(cc)is greater than the conduction threshold level, the sensing circuit willproduce an output at zero or ground level; if lower than the threshold,the output is at the level of V_(cc).

The sensing circuit output operates to switch a bias voltage controlelement including a series resistor and transistor switch between thebias voltage output pad or conductor and ground reference. When renderedconductive by the V_(cc) output level of the sensing circuit, thecontrol element will provide a relatively low resistance path to groundto both rapidly bleed off the injected charges that increase the biasabove a proper operating level and also to provide the desired rapidbias level decay if the V_(cc) level should drop from its high operatinglevel of perhaps six volts to its low operating level of approximatelyfour volts. The control circuitry therefore includes a sensing circuitrythat measures V_(cc) and the bias voltage level, a control element thatprovides a relatively low resistance path from the bias generator toground when the bias voltage level becomes excessive, and alsotranslation circuitry between the sensing circuitry and the controlelement for translating the output voltage of the sensing circuitry tothe proper input level of the control element,

DESCRIPTION OF THE DRAWINGS

In the drawings that illustrate the preferred embodiment of theinvention:

FIG. 1 is a diagram illustrating typical V_(cc) and correspondingsubstrate voltages plotted against various time cycles;

FIG. 2 is a schematic diagram of the bias control circuitry of theinvention; and

FIG. 3 is a table illustrating the operation of the circuitry of FIG. 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

As previously mentioned, on-chip bias voltage generators that providethe necessary negative voltage to the substrate, or back gate of MOStransistor circuit chips, operate from the V_(cc) supply voltage appliedto the chip and for proper operation of the transistor circuits on thechip, the substrate bias voltage generator may produce negative voltagelevels between approximately two volts and three volts when the V_(cc)supply voltage correspondingly varies between its minimum and maximumoperating levels of approximately four and six volts, respectively.

FIG. 1 is a plot of substrate bias voltage, V_(s), for variousconditions of the supply voltage, V_(cc). When V_(cc) is initiallyapplied to the circuit chip at a time, T₀, it rapidly rises to its fullvalue which may be its maximum opeating level 10 occurring at time, T₁.When the rising V_(cc) voltage reaches a level of approximately 2.5volts, the substrate generator may begin to produce its negative biasvoltage, V_(s), which increases slightly nonlinearly to a proper levelof perhaps -4 volts indicated by the reference numeral 12 at time T₁. Ifthe associated transistor circuitry was not operated in a dynamic mode,both V_(cc) and V_(s) would maintain their levels as indicated by thesection of the plotted curves between times T₁ and T₂.

When a circuit chip, such as a microprocessor chip, is in operation, theV_(cc) load changes as indicated by the ripple section 14 between timesT₂ and T₃. During the operation of the chip, the various N and P siliconlayers of each transistor form capacitances with the transistor gatematerial being subjected to rapid voltage variations generally betweenV_(cc) and V_(s) levels. When the N+ polysilicon drops to its low level,it will be driven more negative than the level of the substrate with theresult that it will inject charges into the substrate and drive thesubstrate voltage to a level lower than the optimum bias as indicated bythe section 16 of the V_(s) waveform of FIG. 1. As previously mentioned,this increased bias tends to pinch off conduction of the transistors.Furthermore, since there is an extremely low substrate leakage current,this excessive substrate bias voltage decays at a very slow rate evenafter V_(cc) has been terminated as indicated by the curve 18 of FIG. 1.

The circuitry of the invention eliminates the deleterious effects ofsubstrate charge injection so that at time, T₂, when such injectionwould normally take place, the control circuit will maintain arelatively constant level of V_(s) as indicated by the section 20 ofFIG. 1. If it is assumed that dynamic operation of the chip is stoppedat between times T₃ and T₄, V_(cc) will return to its normal level asindicated by the section 22 and the V_(s) curve will remain at itsconstant desired level as indicated by the section 24.

If the externally applied V_(cc) supply voltage is lowered at time T₄ toits low operating level 26 at time T₅, the control circuit will providethe necessary low resistance current path to reduce the bias voltageV_(s) to its low operating level 28 very shortly after V_(cc) attainsits low level 26. And if V_(cc) is turned off at time T₆, the controlcircuit will rapidly discharge the substrate charges to reduce the levelof V_(s) to zero as indicated by the curved section 30.

FIG. 2 is a schematic diagram of the preferred embodiment of the controlcircuitry of the invention and is comprised of sensing circuitry 32, acontrol element 34 and translation circuitry 36 that translates theoutput voltage of the sensing circuitry 32 to the proper input level ofthe control element 34. Sensing circuitry 32 samples the level ofV_(cc), compares it with the bias voltage level and generates an outputwhenever the sampled V_(cc) level exceeds the V_(s) level.

Sensing circuitry 32 includes a voltage divider between V_(cc) andground reference. The voltage divider includes a resistance 38 coupledto a V_(cc) source and in series with a resistance 40 connected toground. The values of resistors 38 and 40 should be such that a voltageof approximately ten percent of V_(cc) is produced at their junction 42.The junction 42 is connected to the gate of a transistor 44, the sourceof which is at ground potential and the drain of which is connected tothe source of a heavy depletion transistor 46. The drain of transistor46 is coupled to a conductor carrying the V_(cc) supply voltage and itsgate element is connected to its source and the output terminal of thesensing circuit 32. It will be recognized that the series transistors 44and 46 form a conventional inverter circuit and also that the inputvoltage, V_(in), that is ten or eleven percent of V_(cc), is very nearlyequal to the normal threshold voltage, V_(t), of the transistor 44. Aswill be later discussed in connection with FIG. 3, the output voltage,V_(out), of the sensing circuitry 32, taken from the interconnection oftransistors 44 and 46 will vary between zero and V_(cc).

The control element 34 is essentially a current bypass circuit includinga resistor 48 in series with the transistor switch 50 respectivelyconnected between an output conductor of the substrate bias generator 52and ground potential. A transistor 54, which may be either a heavy or alight depletion load transistor, is connected between the output of thesubstrate bias generator 52 and the gate of the transistor 50. The gateof transistor 54 is coupled back to its source and the generator 52 sothat transistor 54 operates as a series diode-resistance which, in theabsence of any other input signals, will maintain a negative biasvoltage on the gate of transistor 50, thereby rendering itnon-conductive.

When non-conductive, transistor 50 has the substrate bias voltage levelapplied to its drain element and also to its gate element. Transistor 50will become conductive when the control voltage applied to its gatebecomes more positive, or less negative, than its drain voltage. Thetranslating circuitry 36 translates the zero and V_(cc) output of thesensing circuitry 32 into a gate voltage, V_(g), that will appropriatelyswitch transistor 50 between its conductive and non-conductive states.In the preferred embodiment, the translation circuitry 36 comprises aseries array of five enhancement transistors 56, 57, 58, 59 and 60. Thesource of each transistor is connected to the drain of each previoustransistor to form the series array and the gate element of each of thetransistors 56-60 is connected to its own drain element so that thetransistors become diodes forward biased between the sensing circuitry32 and the control element 34. The purpose of the diode string 56-60 isto reduce the output voltage V_(out), when at the V_(cc) level, to aproper gate voltage, V_(g), that will control the switching transistor50. If each of the diode-connected transistors 56-60 has a normalthreshold voltage of 0.7 volts, the translation circuitry 36 willprovide a 3.5 volt drop between V_(out) and V_(g).

The translation circuitry 36 illustrated in FIG. 2 is the preferredembodiment since it is very simple to deposit on a circuit board chip.It must be understood that other translation circuits will also providethe necessary voltage level transferred between the sensing circuitry 32and the control element 34. For example, the control element 34 may beproperly operated by substituting a translation circuitry comprising asingle capacitor. In this configuration, the transistor 54 may beeliminated and an enhancement transistor should be diode connected withthe drain and gate elements coupled to the gate of transistor 50 and thesource element at ground. In such a configuration, the transistor 50 isnormally non-conductive and a high level V_(out) will cause acorrresponding positive jump in V_(g) to render transistor 50conductive. When V_(out) drops to its low level, or zero volts, thecapacitor plate on the control circuit side will discharge through thediode to ground, thereby permitting transistor 50 to becomenon-conductive.

FIG. 3 is a table illustrating the various levels and conditions of thecircuitry of FIG. 2 at different values of V_(cc) supply voltage and ofthe substrate voltage V_(s). If the externally supplied V_(cc) level is4.0 volts, the voltage divider resistors 38 and 40 supply a V_(in) of0.4 volts to the gate of transistor 44. The transistor 44 is a componentpart of the circuit chip and is subjected to the substrate voltageV_(s). The conduction threshold V_(t) of transistor 44 varies accordingto the substrate bias voltage, V_(s). Thus, if V_(s) is -2.0 volts, -3.0volts, or -4.0 volts, the threshold voltage V_(t), of the transistor 44may respectively vary between 0.4 volts, 0.5 volts, or 0.6 volts.Transistor 44 compares V_(in) with V_(t). If V_(in) is more positivethan V_(t), transistor 44 conducts to produce a V_(out) of zero volts.Whenever V_(in) is less positive than V_(t), transistor 44 is off,thereby lifting its output conductor from ground and producing V_(out)substantially equal to V_(cc). When V_(in) is substantially equal toV_(t), the conduction of transistor 44 is unpredictable and variesbetween its on and off state to produce a V_(out) that correspondinglyvaries between zero and V_(cc) as indicated by the dash in the top ofthe "44" column of FIG. 3.

The translation circuitry 36 comprising the series string ofdiode-connected transistors 56-60 is forward biased to provide a voltagedrop of 3.5 volts when V_(out) is equal to V_(cc). Therefore, whenV_(cc) is equal to 4.0 volts, and transistor 44 is not conducting, V_(g)will be equal to 4.0 volts less the drop in the translation circuitry36, or 0.5 volts. Since this voltage is more positive than the lowestvoltage appearing on the source or drain of transistor 50, transistor 50will turn on to bypass charges from the substrate, thereby lowering thesubstrate bias voltage. If, on the other hand, V_(in) is more positivethan V_(t) and transistor 44 is on, V_(out) will be set at ground orzero volts and the difference between V_(out) and the substrate biaslevel V_(s) that normally applied to the non-conducting transistor 50,will be insufficient to permit conduction through the translationcircuitry 36. Therefore, V_(g) will remain unchanged at the V_(s) levelto maintain transistor 50 in its off condition.

FIG. 3 illustrates various voltage levels and transistor conductionconditions for three values of supply voltage, V_(cc) and substratebias, V_(s). The vertical columns labeled 44 and 50 indicate the ON, theOFF, or the varying unpredictable switching conditions of thetransistors 44 and 50. It will be noted that whenever V_(in) is morepositive than V_(t), at any level of V_(cc), transistor 44 is on andtransistor 50 is off. Whenever V_(in) is less positive than V_(t),transistor 44 is off and transistor 50 is on to provide the chargebypass that permits the bias voltage to follow the desired responsecurve illustrated by the sections 20, 24, 28 and 30 of FIG. 1. Wheneverthe level of V_(in) is substantially equal to V_(t), transistor 44 willrapidly and unpredictably vary between an on and off condition andtransistor 50 will vary off and on, respectively, as indicated by thedashes in the table of FIG. 3.

Having thus described my invention, what is claimed is:
 1. Control circuitry for limiting bias voltage levels at the substrate of a transistor circuit chip, said control circuitry comprising:sensing circuitry means responsive to variations in the circuit chip supply voltage level and to the chip substrate bias voltage level for producing an output signal corresponding to said supply voltage level whenever said bias voltage exceeds a predetermined level for a particular level of said supply voltage; a switching transistor in series with a resistance coupled between a bias voltage conductor and ground reference, said switching transistor being responsive to the occurrence of said output signal for coupling said conductor with said ground reference; and a resistive element coupled between said bias voltage conductor and the control element of said switching transistor for maintaining said transistor in a normally non-conductive state in the absence of said output signal.
 2. The control circuitry claimed in claim 1 further including translation circuitry coupled between the output terminal of said sensing circuitry means and the control element of said switching transistor for translating said output signal into a control gate voltage for switching said switching transistor.
 3. The control circuitry claimed in claim 1 wherein said sensing circuitry means includes a transistor inverter comprising first and second series transistors coupled between a circuit chip supply voltage conductor and ground reference, said first and second transistors being constructed on said circuit chip and being subjected to said substrate bias voltage.
 4. The control circuitry claimed in claim 3 wherein said sensing circuitry means further includes a voltage divider circuit between said circuit supply voltage and said ground reference, said voltage divider being tapped to provide an input signal to said first transistor of said inverter that is approximately one-tenth the level of said chip supply voltage.
 5. The control circuitry claimed in claim 4 wherein said inverter responds to said input voltage signal and to said bias voltage level to produce a high level output signal whenever said input voltage signal is less positive than the conduction threshold voltage level of said first transistor.
 6. The control circuitry claimed in claim 5 wherein said inverter produces an output signal at a high level substantially equal to said chip supply voltage level, said output signal being substantially at ground reference in the absence of said high level output signal.
 7. The control circuitry claimed in claim 6 further including translation circuitry coupled between the output of said inverter and the gate electrode of said control element of said switching transistor, said translating circuitry providing switching transistor gate voltage levels that will turn on said switching transistor at said high level output signal and will permit said bias voltage level to retain said switching transistor in a non-conductive state at low ground reference output levels of said inverter.
 8. The control circuitry claimed in claim 7 wherein said translation circuitry includes a plurality of diode connected transistors in series, the quantity of transistors in said plurality being sufficient to render said translation transistors non-conductive at voltage level differences between said low level ground reference output signal and said bias voltage level at said non-conductive switching transistor, and for translating said high level output signals into a conduction producing control gate signal at said switching transistor.
 9. The control circuitry claimed in claim 7 wherein said translation circuitry includes a capacitor coupled between the output terminal of said inverter and the gate of said switching transistor, said translation circuitry further including a diode connected transistor between the gate of said switching transistor and ground reference for discharging said capacitor in the absence of a high level output signal from said inverter. 